By Keliu Shu, Edgar Sanchez-Sinencio
This ebook offers either basics and the state-of-the-art of PLL synthesizer layout and research strategies. an entire review of either system-level and circuit-level layout and research are lined. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is carried out in 0.35m m CMOS. It contains a high-speed and strong phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on pace and integration bottlenecks of PLL synthesizer elegantly. This ebook is conceived as a PLL synthesizer handbook for either academia researchers and layout engineers.
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Extra info for CMOS PLL Synthesizers: Analysis and Design
Example text
Savaria, “Direct digital frequency synthesis of low-jitter clocks,” IEEE J. Solid-State Circuits, vol. 36, pp. 570-572, Mar. 2001 [30] S. Liu, T. Yu, and H. Tsao, “Pipeline direct digital frequency synthesizer using decomposition method,” IEE Proc. Circuits Devices Syst, vol. 48, June 2001 [31] A. Sodagar and G. Lahiji, “A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation,” IEEE Trans. Circuits Syst. II, vol. 48, pp.
The divide ratio of the dual-modulus prescaler is P or P+1. M and A are programmable integers [2], [3]. Each divider output cycle consists of (P+1)·A+P·(M–A) VCO cycles. Thus the nominal frequency divide ratio is: The synthesizer output frequency is Chapter 3 32 Figure 3-1. Charge-pump PLL frequency synthesizer Figure 3-2. Tri-state phase-frequency detector (PFD) The phase detector (PD) detects the phase difference between the reference signal and the feedback signal from the VCO and frequency divider.
Razavi, Monolithic Phase-locked Loops and Clock Recovery Circuits. New York: IEEE Press, 1996 This page intentionally left blank Chapter 3 PLL FREQUENCY SYNTHESIZER This chapter presents the analysis of PLL-based frequency synthesizers. It includes the continuous-time linear analysis, discrete-time analysis, operation modes, stability, and fast-locking techniques. An integer-N PLL synthesizer design example is given to illustrate the system-level parameter design procedure. 1 Basic building blocks of charge-pump PLL The block diagram of the PLL frequency synthesizer is shown in Fig.